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| Ordering number :EN5544 CMOS LSI LC72P366 On-Chip One-Time Programmable PROM Single-Chip PLL Controller Overview The LC72P366 is a single-chip PLL-plus-controller onetime programmable PROM microcontroller that corresponds to the Sanyo LC72358N, LC72362N, and LC72366. The LC72P366 has the same package and pin assignment as the LC72358N, LC72362N, and LC72366 mask ROM versions, and provides 32 KB of on-chip PROM, organized as 16k words by 16 bits. The LC72P366 can prove useful in reducing the startup times for initial production runs and for reducing the switchover time when end-product specifications change. Package Dimensions unit: mm 3174-QFP80E [LC72P366] Features * 32 KB (16k words x 16 bits) of on-chip PROM -- This is a one-time programmable 32 KB (16k-word x 16-bit) PROM. * Pin compatible with the mask ROM versions, i.e. identical package and pin assignment. Writing Sanyo ROMs Sanyo provides a for-fee ROM writing service that consists of writing data to the PROM in one-time programmable PROM microcontrollers, printing, screening, and data readout verification. Contact your Sanyo sales representative for details. SANYO: QIP80E * CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN N3096HA (OT) No. 5544-1/14 LC72P366 Pin Assignment No. 5544-2/14 LC72P366 Block Diagram No. 5544-3/14 LC72P366 Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Maximum supply voltage Input voltage Output voltage Symbol VDD max VIN VOUT(1) VOUT(2) IOUT(1) Output current IOUT(2) IOUT(3) Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg All input pins Port J All output ports other than VOUT(1) Port J Ports D, E, F, G, K, L, M, N, O, P, and Q, EO1, EO2, EO3, SUBPD Ports B and C Ta = -30 to +70C Conditions Ratings -0.3 to +6.5 -0.3 to VDD +0.3 -0.3 to +15 -0.3 to VDD +0.3 0 to +5 0 to +3 0 to +1 400 -30 to +70 -45 to +125 Unit V V V V mA mA mA mW C C Allowable Operating Ranges at Ta = -30 to +70C, VDD = 3.5 to 5.5 V Parameter Symbol VDD(1) Supply voltage VDD(2) VDD(3) VIH(1) Input high-level voltage VIH(2) VIH(3) VIH(4) VIL(1) Input low-level voltage VIL(2) VIL(3) VIL(4) fIN(1) fIN(2) fIN(3) fIN(4) Input frequency fIN(5) fIN(6) fIN(7) fIN(8) VIN(1) Input amplitude VIN(2) VIN(3) Input voltage range VIN(4) Conditions CPU and PLL circuit operating CPU operating Memory retention voltage Ports E, H, I, L, M, and Q, HCTR, LCTR (when selected for input) Ports F, G, and K, LCTR (in period measurement mode), HOLD SNS Port A Ports E, H, I, L, M, and Q, HCTR, LCTR (when selected for input) Ports A, F, G, and K, LCTR (in period measurement mode) SNS HOLD XIN FMIN : VIN(2), VDD(1) FMIN : VIN(3), VDD(1) AMIN(H) : VIN(3), VDD(1) AMIN(L) : VIN(3), VDD(1) HCTR : VIN(3), VDD(1) LCTR : VIN(3), VDD(1) LCTR (in period measurement mode): VIH(2), VIL(2), VDD(1) XIN FMIN FMIN, AMIN, HCTR, LCTR ADI0 to ADI5 Ratings min 4.5 4.0 1.3 0.7 VDD 0.8 VDD 2.5 0.6 VDD 0 0 0 0 4.0 10 10 2.0 0.5 0.4 100 1 0.5 0.10 0.07 0 4.5 typ 5.0 max 5.5 5.5 5.5 VDD VDD VDD VDD 0.3 VDD 0.2 VDD 1.3 0.4 VDD 5.0 150 130 40 10 12 500 20 x 103 1.5 1.5 1.5 VDD Unit V V V V V V V V V V V MHz MHz MHz MHz MHz MHz kHz Hz Vrms Vrms Vrms V No. 5544-4/14 LC72P366 Electrical Characteristics in the Allowable Operating Ranges Parameter Symbol IIH(1) IIH(2) Input high-level current Conditions XIN : VI = VDD = 5.0 V FMIN, AMIN, HCTR, LCTR : VI = VDD = 5.0 V Ports A, E, F, G, H, I, K, L, M, and Q, SNS, HOLD, HCTR, LCTR, and with no pull-down resistor on port A, VI = VDD = 5.0 V With input mode selected for ports E, F, G, K, L, M, and Q Port A: pull-down resistor present XIN:VI = VSS FMIN, AMIN, HCTR, LCTR : VSS Ports A, E, F, G, H, I, K, L, M, and Q, SNS, HOLD, HCTR, LCTR, and with no pull-down resistor on port A, VI = VSS With input mode selected for ports E, F, G, K, L, M, and Q Port A: pull-down resistor present Port A: pull-down resistor present VDD = 5 V TEST1, TEST2 Ports F, G, and K, LCTR (in period measurement mode) Ports B and C: IO = -1 mA Ports D, E, F, G, K, L, M, N, O, P, and Q: IO = -1 mA EO1, EO2, EO3, SUBPD : IO = -500 A XOUT : IO = -200 A Ports B and C: IO = 50 A Ports D, E, F, G, K, L, M, N, O, P, and Q: IO = 1 mA EO1, EO2, EO3, SUBPD : IO = 500 A XOUT : IO = 200 A Port J: IO = 5 mA Ports B, C, D, E, F, G, K, L, M, N, O, P, and Q EO1, EO2, EO3, SUBPD Port J ADI0 to ADI5 : VDD(1) PREJ VDET IDD(1) IDD(2) Current drain IDD(3) IDD(4) VDD(1) : fIN(2) = 130 MHz, Ta = 25C VDD(2): halt mode*, Ta = 25C (See figure 1.) VDD = 5.5 V, oscillator stopped Ta = 25C (See figure 2.) VDD = 2.5 V, oscillator stopped Ta = 25C (See figure 2.) SNS 3.0 3.5 12 0.45 5 1 -3.0 -100 -5.0 -1/2 0.1 VDD VDD - 2.0 VDD - 1.0 VDD - 1.0 VDD - 1.0 1.0 2.0 1.0 1.0 1.5 2.0 +3.0 +100 +5.0 +1/2 50 4.0 24 V A nA A LSB s V mA mA A A 75 100 10 0.2 VDD VDD - 1.0 2.0 4.0 50 5.0 10 15 30 Ratings min 2.0 4.0 typ 5.0 10 max 15 30 Unit A A IIH(3) 3.0 A IIH(4) IIL(1) IIL(2) Input low-level current IIL(3) A A A 3.0 A Input floating voltage Pull-down resistance Hysteresis VIF RPD(1) RPD(2) VH VOH(1) VOH(2) VOH(3) VOH(4) VOL(1) VOL(2) 0.05 VDD 200 V k k V V V V V V V Output high-level voltage Output low-level voltage VOL(3) VOL(4) VOL(5) IOFF(1) Output off leakage current IOFF(2) IOFF(3) A/D conversion error Rejected pulse width Power down detection voltage Note: * Executing 20 STEP instructions every millisecond. With the PLL and counter circuits stopped. Test Circuit Diagrams Note: With PB to PG, and PJ to PQ all open. However, with PE to PG, PK to PM, and PQ selected for output. Note: With PA to PQ all open. Figure 1 IDD(2) in Halt Mode Figure 2 IDD(3) and IDD(4) in Backup Mode No. 5544-5/14 LC72P366 Pin Functions Pin No. Symbol I/O I/O type Function Key return signal input-only ports. The threshold voltage is set to a relatively low value. When a key matrix is formed in combination with the PB and PC ports, up to three simultaneous key presses can be detected. The pull-down resistors are set by the IOS instruction with PWn = 2 for all four pins at the same time and cannot be set on an individual pin basis. Input is disabled in clock stop mode. 30 29 28 27 PA0 PA1 PA2 PA3 I Pull-down resistor included Input 26 25 24 23 22 21 20 19 18 17 16 15 PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 PD0 PD1 PD2 PD3 O CMOS push-pull Output-only ports. In clock stop mode, these pins go to the output high-impedance state. During the power-on reset, these pins go to the output high-impedance state and hold that state until an output instruction is executed. O Unbalanced CMOS push-pull Key source signal output-only ports. Since the output transistor circuit is an unbalanced CMOS structure, diodes to prevent shorting due to multiple key presses are not required. In clock stop mode, these pins go to the output high-impedance state. During the power-on reset, these pins go to the output high-impedance state and hold that state until an output instruction is executed. 14 13 12 11 10 9 8 7 6 5 4 3 PE0 PE1/SCK2 PE2/SO2 PE3/SI2 PF0 PF1/SCK1 PF2/SO1 PF3/SI1 PG0 PG1/SCK0 PG2/SO0 PG3/SI0 I/O CMOS push-pull General-purpose I/O port/serial I/O pin shared-function ports. The F and G port inputs are Schmitt inputs. The E ports is a normal input. The IOS instruction switches these ports between general-purpose I/O ports and serial I/O ports, and between input and output for general-purpose I/O ports. * When used as general-purpose I/O ports these pins: Can be set for input or output in bit units (bit I/O), and are set for use as general-purpose I/O ports by the IOS instruction with PWn = 0. b0 = SI/O 0 0 ...................general-purpose port b1 = SI/O 1 1 ...................SI/O port b2 = SI/O 2 are set for input or output by the IOS instruction in bit units. PE..............PWn = 4 0 ...................Input PF..............PWn = 5 1 ...................Output PG .............PWn = 6 * When used as serial I/O ports these pins: Are set for serial I/O port use by the IOS instruction with PWn = 0, and are accessed by reading and writing the serial I/O data buffer with the INR and OUTR instructions. Note: Pin setup states when used as serial I/O ports: PE0, PF0, PG0 ......General-purpose I/O PE1, PF1, PG1 ......SCK output in internal clock mode SCK input in external clock mode PE2, PF2, PG2......SO output PE3, PF3, PG3......SI input In clock stop mode, input is disabled and these pins go to the high-impedance state. During the power-on reset, these pins become general-purpose input ports. 1 80 XIN XOUT I O -- Connections for a 4.5 MHz crystal oscillator 78 77 EO1 EO2 O CMOS tristate Main charge pump outputs These pins output a high level when the frequency generated by dividing the local oscillator signal frequency by N is higher than the reference frequency, and a low level when that frequency is lower. These pins go to the high-impedance state when the frequencies match. These pins go to the high-impedance state when the HOLD pin is set low in the hold enable state. In clock stop mode, during the power-on reset and in the PLL stop state, these pins go to the high-impedance state. Continued on next page. No. 5544-6/14 LC72P366 Continued from preceding page. Pin No. 76 73 31 Symbol VSS VDD VDD -- -- Power supply connections I/O I/O type Function 75 FMIN I Input FM VCO (local oscillator) input This pin is selected by the PLL instruction CW1 (b1, b0 are ignored). Capacitor coupling must be used for signal input. Input is disabled when the HOLD pin is set low in the hold enable state. Input is disabled in clock stop mode, during the power-on reset, and in the PLL stop state. AM VCO (local oscillator) input This pin is selected and the band set by the PLL instruction CW1 (b1, b0). b1 74 AMIN I Input 1 1 b0 0 1 Band 2 to 40 MHz (SW) 0.5 to 10 MHz (MW, LW) Capacitor coupling must be used for signal input. Input is disabled when the HOLD pin is set low in the hold enable state. Input is disabled in clock stop mode, during the power-on reset, and in the PLL stop state. Sub-charge pump output This pin, in combination with the main charge pump, allows the construction of a highspeed locking circuit. The DZC instruction controls the sub-charge pump. b3 0 0 72 SUBPD O CMOS tristate 1 1 b2 0 1 0 1 High impedance Only operates in the unlocked state (450 kHz) Only operates in the unlocked state (900 kHz) Normal operation Operation This pin goes to the high-impedance state when the HOLD pin is set low in the hold enable state. This pin goes to the high-impedance state in clock stop mode, during the power-on reset, and in the PLL stop state. 71 EO3 O CMOS tristate Second PLL charge pump output This pin outputs a low level when the frequency generated by dividing the local oscillator signal frequency by N is higher than the reference frequency, and a high level when that frequency is lower. This pin goes to the high-impedance state when the frequencies match. (Note that this pin's output logic is the opposite of that of the EO1 and EO2 pins.) This pin goes to the high-impedance state when the HOLD pin is set low in the hold enable state. This pin goes to the high-impedance state in clock stop mode, during the power-on reset, and in the PLL stop state. Continued on next page. No. 5544-7/14 LC72P366 Continued from preceding page. Pin No. Symbol I/O I/O type Function 70 HCTR I Input Universal counter/general-purpose input shared-function input port The IOS instruction b3 with PWn = 3 switches the pin function between universal counter input and general-purpose input. * Frequency measurement The universal counter function is selected by an IOS instruction with PWn = 3 and b3 = 0. HCTR frequency measurement mode is set up by a UCS instruction with b3 = 0 and b2 = 0, and counting is started with a UCC instruction after the count time is selected. The CNTEND flag is set when the count completes. To operate this circuit as an AC amplifier in this mode, the input must be capacitor coupled. * General-purpose input pin use The general-purpose input port function is selected by an IOS instruction with PWn = 3 and b3 = 1. An internal register (address: 0EH) input instruction INR (b0) is used to acquire data from this pin. Input is disabled in clock stop mode. (The input pin will be pulled down.) During the power-on reset, the universal counter function is selected. 69 LCTR I Input Universal counter (frequency and period measurement)/general-purpose input sharedfunction input port The IOS instruction b2 with PWn = 3 switches the pin function between universal counter input and general-purpose input. * Frequency measurement The universal counter function is selected by an IOS instruction with PWn = 3 and b2 = 0. LCTR frequency measurement mode is set up by a UCS instruction with b3 = 0 b2 = 1, and counting is started with a UCC instruction after the count time is selected. The CNTEND flag is set when the count completes. To operate this circuit as an AC amplifier in this mode, the input must be capacitor coupled. * Period measurement With the universal counter function selected, set up period measurement mode with a UCS instruction with b3 = 1 and b2 = 0, and start the count with a UCC instruction after selecting the count time. The CNTEND flag will be set when the count completes. In this mode, the signal must be input with DC coupling to turn off the bias feedback resistor. * General-purpose input pin use The general-purpose input port function is selected by an IOS instruction with PWn = 3, b2 = 1. An internal register (address: 0EH) input instruction INR (b1) is used to acquire data from this pin. Input is disabled in clock stop mode. (The input pin will be pulled down.) During the power-on reset, the universal counter function (in HCTR frequency measurement mode) is selected. 68 SNS I Input Voltage sense/general-purpose input pin shared-function port This circuit is designed for a relatively low input threshold voltage. * Voltage sense pin usage This input pin is used to determine whether or not a power failure occurred after recovery from backup (clock stop) mode. An internal sense F/F is used for this determination. The sense F/F is tested with a TUL instruction (b2). * General-purpose input port usage When used as a general-purpose input port, the state is sensed by using a TUL instruction (b3). Since, unlike other input ports, input is not disabled in clock stop mode and during the power-on reset, special care is required with respect to through currents. Continued on next page. No. 5544-8/14 LC72P366 Continued from preceding page. Pin No. Symbol I/O I/O type Function PLL control and clock stop mode control Setting this pin low in the hold enabled state disables input to the FMIN and AMIN pins and sets the EO pin to the high-impedance state. To enter clock stop mode, set the HOLDEN flag, set this pin low, and execute a CKSTP instruction. To clear clock stop mode, set this pin high. 67 HOLD I Input 66 65 64 63 62 61 PH0/ADI0 PH1/ADI1 PH2/ADI2 PH3/ADI3 PI0/ADI4 PI1/ADI5 I Input General-purpose input port/A/D converter shared-function pins The IOS instruction with PWn = 7 or 8 switches the pin function between general-purpose input ports and A/D converter inputs. * General-purpose input port usage Specify general-purpose input port usage with the IOS instruction with PWn = 7 or 8 in bit units. * A/D converter usage Specify A/D converter usage with the IOS instruction with PWn = 7 or 8 in bit units. Specify the pin to convert with the IOS instruction with PWn = 1. Start a conversion with the UCC instruction (b2). The ADCE flag will be set when the conversion competes. Note: Executing an input instruction for a port specified for ADI usage will always return low since input is disabled. These pins must be set up for general-purpose input port usage before an input instruction is executed. Input is disabled in clock stop mode. During the power-on reset, these pins go to the general-purpose input port function. 60 59 58 57 PJ0 PJ1 PJ2 PJ3 O N-channel open drain General-purpose output ports An external pull-up resistor is required since these pins are open-drain circuits. In clock stop mode, these pins go to the transistor off state (high level output). During the power-on reset, these pins are set up as general-purpose output ports and go to the transistor off state (high level output). 56 55 54 53 PK0/INT0 PK1/INT1 PK2 PK3 I/O CMOS push-pull General-purpose I/O/external interrupt shared-function ports There is no instruction that switches the function of these ports between general-purpose ports and external interrupt ports. These pins function as external interrupt pins at the point where the external interrupt enable flag is set. * General-purpose I/O port usage These pins can be set for input or output in bit units (bit I/O). The IOS instruction is used to specify input or output in bit units. * External interrupt pin usage This function can be used by setting the external interrupt enable flags (INT0EN and INT1EN) in status register 2. The corresponding pin must be set up for input. To enable interrupt operation, the interrupt enable flag (INTEN) in status register 1 also must be set. The IOS instruction with PWn = 3, b1 = INT1, and b0 = INT0 is used to select rising or falling edge detection. In clock stop mode, input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports. 52 to 45 PL0 to PL3 PM0 to PM3 I/O CMOS push-pull General-purpose I/O ports The IOS instruction is used to specify input or output. In clock stop mode input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports. Continued on next page. No. 5544-9/14 LC72P366 Continued from preceding page. Pin No. Symbol I/O I/O type Function 44 43 42 41 PN0/BEEP PN1 PN2 PN3 O CMOS push-pull General-purpose output port/BEEP tone shared-function output pins The BEEP instruction switches between the general-purpose output port and BEEP tone functions. * General-purpose output port usage The BEEP instruction with b3 = 0 sets up the general-purpose output port function. Pins PN1 to PN3 are general-purpose output-only pins. * BEEP output usage The BEEP instruction with b3 = 1 sets up BEEP output. The BEEP instruction bits b0, b1 and b2 sets the frequency. When set up as the BEEP port, executing an output instruction will set the internal latch data but has no influence on the output. These pins go to the output high-impedance state in clock stop mode. These pins go to the output high-impedance state during the power-on reset and hold that state until an output instruction is executed. 40 to 33 PO0 to PO3 PP0 to PP3 O CMOS push-pull Output-only ports These pins go to the output high-impedance state in clock stop mode. These pins go to the output high-impedance state during the power-on reset and hold that state until an output instruction is executed. 32 PQ0 I/O CMOS push-pull General-purpose I/O ports The IOS instruction is used to specify input or output. The OUTR and INR instructions are used for output and input. The bit set, reset and test instruction cannot be used. In clock stop mode input is disabled and these pins go to the high impedance state. During the power-on reset, these pins function as general-purpose input ports. 79 2 TEST1 TEST2 LSI test pins These pins must be either left open or connected to ground. Usage Notes The LC72P366 is provided for use in initial shipments of products designed to use the Sanyo LC72358N, LC72362N, or LC72366. Keep the following points in mind when using this product. * Differences between the LC72P366 and the LC72358N, LC72362N, and LC72366 Parameter Operating temperature LC72P366 -30 to +70C Minimum 4.0 V CPU operating voltage Typical Maximum 5.5 V Minimum 3.0 V Power down detection voltage (VDET) Typical 3.5 V Maximum 4.0 V LC72358N, 72362N, 72366 -40 to +85C Minimum 3.5 V Typical Maximum 5.5 V Minimum 2.7 V Typical 3.0 V Maximum 3.3 V * ROM ordering procedure when using Sanyo's for-fee PROM programming service -- When ordering one-time programmable versions and mask versions at the same time: The customer must provide the mask ROM version program, the mask ROM version order forms, and the one-time programmable version order forms. -- When order just the one-time programmable version: The customer must provide the one-time programmable version program and the one-time programmable version order forms. No. 5544-10/14 LC72P366 * Conditions required for mounting the LC72P366 1. Products programmed by the user: Mount the LC72P366 using the following procedure when using products shipped from Sanyo without the PROM having been programmed. 2. Products programmed by Sanyo: Mount the LC72P366 using the following procedure when using products shipped from Sanyo with the PROM programmed by Sanyo. [Caution] * Due to the nature of the product, it is not possible for Sanyo to fully test one-time programmable PROM microcontrollers (i.e., products with blank PROMs) before shipment to the customer. This means that there will be some amount of yield reduction after programming. Usage Procedures * Programming the on-chip PROM There are two methods for writing the LC72P366 on-chip PROM as follows: -- Using a general-purpose PROM programmer A general-purpose PROM programmer can be used if a special-purpose PROM programming adapter (product name: LC72P366 EPROM PROGRAMMER) is used. The write procedure used is the 27512 or 27C512 (with Vpp = 12.5 V) Intel fast write method. Specify 0000H to 7FFFH as the address settings. -- Using the RE32N in-circuit emulator: The RE32N in-circuit emulator can be used if a special-purpose PROM programming adapter (product name: LC72P366 RE32N) is used. Use the PGOTP command as the write method. * Special-purpose writing adapters Since there are two special-purpose PROM programming adapters as mentioned above, the correct adapter must be used. General-purpose EPROM programmer adapter In-circuit emulator RE32 adapter : Product name LC72P366 EPROM PROGRAMMER : Catalog no. NDK-DC-018 : Product name LC72P366 RE32N : Catalog no. NDK-DC-020 No. 5544-11/14 LC72P366 LC72P366 Instruction Overview Abbreviations : ADDR : Program memory address b : Borrow C : Carry DH : Data memory address high (Row address) [2 bits] DL : Data memory address low (Column address) [4 bits] I : Immediate data [4 bits] M : Data Memory address N : Bit position [4 bits] Pn : Port number [4 bits] PWn : Port control word number [4 bits] r : General register (on of location 00 to 0FH in the current bank) Rn : Register number [4 bits] () : Contents of register or memory ( )n : Contents of bit N of register or memory Instruction group Operand Mnemonic AD ADS 1st r r r r M M M M r r r r 2nd M M M M I I I I M M M M Function Add M to r Add M to r, then skip if carry Add M to r with carry Add M to r with carry, then skip if carry Add I to M Add I to M, then skip if carry Add I to M with carry Add I to M with carry, then skip if carry Subtract M from r Subtract M from r, then skip if borrow Subtract M from r with borrow Subtract M from r with borrow, then skip if borrow Subtract I from M Subtract I from M, then skip if borrow Subtract I from M with borrow Subtract I from M with borrow, then skip if borrow Skip if r equal to M Skip if M equal to I Skip if M not equal to I Skip if r is greater than or equal to M Operation r (r) + (M) r (r) + (M) skip if carry r (r) + (M) + C r (r) + (M) + C skip if carry M (M) + I M (M) + I skip if carry M (M) + I + C M (M) + I+ C skip if carry r (r) - (M) r (r) - (M) skip if borrow r (r) - (M) - b r (r) - (M) - b skip if borrow M (M) - I M (M) - I skip if borrow M (M) - I - b M (M) - I - b skip if borrow (r) - (M) skip if zero (M) - I skip if zero (M) - I skip if not zero (r) - (M) skip if not borrow D15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Machine code 9 DH DH DH DH DH DH DH DH DH DH DH DH 8 7 6 DL DL DL DL DL DL DL DL DL DL DL DL 5 4 3 2 r r r r I I I I r r r I 1 D0 Addition instructions Subtraction instructions AC ACS AI AIS AIC AICS SU SUS SB SBS SI SIS SIB SIBS M M M M I I I I 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 DH DH DH DH DL DL DL DL I I I I Comparison instructions SEQ SEQI SNEI SGE SGEI SLEI r M M r M M M I I M I I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 1 1 0 1 1 0 1 1 DH DH DH DH DH DH DL DL DL DL DL DL r I I r I I Skip if M is greater than (M) - I or equal to I skip if not borrow Skip if M is less than I (M) - I skip if zero Continued on next page. No. 5544-12/14 LC72P366 Continued from preceding page. Instruction group Operand Mnemonic AND 1st r M r M r M r r M r M r M 2n M I M I M I Function AND M with r AND I with M OR M with r OR I with M Exclusive OR I with r Exclusive OR I with M Shift r right with carry Load M to r Store r to M Move M to destinsation M referring to r in the same row Move M to destinsation M referring to r in the same row Operation r (r) AND (M) M (M) AND I r (r) OR (M) M (M) OR I r (r) XOR I M (M) XOR I carry (r) v v Machine code D15 14 13 12 11 10 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 0 0 DH DH DH 9 DH DH DH DH DH DH 0 1 1 DL DL DL 8 7 6 DL DL DL DL DL DL 1 0 5 4 3 2 r I r r r I r r r r 1 D0 Logical instructions ANDI OR ORI EXL EXLI SHR LD ST r (M) M (r) [DH, rn] (M) Transfer instructions MVRD MVRS M r M [DH, rn] 1 1 0 1 1 1 DH DL r MVSR MVI TMT M1 M M M2 I N Move source M referring [DH, DL1] [DH, DL2] to r to M in the same row Move I to M Test M bits, then skip if all bits specified are true Test M bits, then skip if all bits specified are false Jump to the address Call subroutine Return from subroutine Return from subroutine and skip Return from subroutine with bank data MI if M (N) = all "1", then skip if M (N) = all "0", then skip PC ADDR Stack (PC) + 1 PC Stack PC Stack + 1 PC Stack BANK Stack 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 1 0 DH DH DH DL1 DL DL DL2 I N Bit test instructions TMF M N 1 1 1 1 0 1 DH DL N JMP Jump and subroutine instructions CAL RT RTS RTB RTBS RTI ADDR ADDR 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 ADDR (14 bits) ADDR (12 bits) 0 0 1 1 0 1 1 1 1 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 Return from subroutine PC Stack + 1 with bank data and skip BANK Stack Return from interrupt PC Stack BANK Stack CARRY Stack (Status reg I) N 1 (Status reg I) N 0 if (Status reg I) N = all "1", then skip if (Status reg I) N = "0", then skip if Unlock FF (N) = all "0", then skip PLL reg PLL data M (Rn reg) Rn reg (M) SS Status register instructions RS TST TSF TUL I I I I N N N N N Set status register Reset status register Test status register true Test status register false Test unlock F/F then skip if it has not been set 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 I I 0 I I N N N N Internal register F/F test transfer instructions instructions 1 N PLL INR OUTR M M M r Rn Rn Load M to PLL register Input register/port data to M Output contents of M to register/port 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 0 1 DH DH DH DL DL DL r Rn Rn Continued on next page. No. 5544-13/14 LC72P366 Continued from preceding page. Instruction group Operand Mnemonic SIO 1st I1 I I I I N PWn M M Pn Pn Pn N Pn Pn N N N 2n I2 Function Serial I/O control Set I to UCCW1 Set I to UCCW2 Beep control Dead zone control Set timer register Set port control word Input port data to M Output contents of M to port Set port bits Reset port bits Test port bit, then skip if all bits specified are true Test port bits, then skip if all bits specified are false Select Bank Operation SIO reg I1,I2 UCCW1 I UCCW2 I BEEP reg I DZC reg I Timer reg I IOS reg PWn N M (Pn) Pn M (Pn) N 1 (Pn) N 0 if (Pn) N = all "1", then skip if (Pn) N = all "0", then skip BANK I D15 14 13 12 11 10 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 Machine code 9 0 0 0 0 0 0 1 DH DH 1 1 0 0 1 0 8 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 7 6 I1 0 1 1 1 0 1 0 0 1 0 5 4 3 2 I2 I I I I N N Pn Pn N N N 1 D0 Hardware control instructions UCS UCC BEEP DZC TMS IOS IN OUT PWn DL DL Pn Pn Pn I/O instructions SPB RPB TPT TPF Pn N 1 1 1 1 1 1 0 1 Pn N Bank switching instructions BANK I 0 0 0 0 0 0 0 0 0 1 1 1 I Other instructions HALT CKSTP NOP I Halt mode control Clock stop No operation HALT reg I, then CPU click stop stop X'tal OSC if HOLD = 0 No operation 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 I s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1996. Specifications and information herein are subject to change without notice. No. 5544-14/14 |
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